Xen fixes and cleanups for x86/64 guests.
Signed-off-by: Keir Fraser <keir@xensource.com>
__asm__ __volatile__ (
TRAP_INSTR
: "=a" (ret) : "0" (__HYPERVISOR_set_timer_op),
- "b" (timeout_hi), "c" (timeout_lo) : "memory" );
+ "b" (timeout_lo), "c" (timeout_hi) : "memory" );
return ret;
}
spin_unlock_irqrestore(&update_lock, flags);
}
-void xen_load_gs(unsigned long ptr)
-{
- int cpu = smp_processor_id();
- int idx;
- unsigned long flags;
- spin_lock_irqsave(&update_lock, flags);
- idx = per_cpu(mmu_update_queue_idx, cpu);
- per_cpu(update_queue[idx], cpu).ptr = phys_to_machine(ptr);
- per_cpu(update_queue[idx], cpu).ptr |= MMU_EXTENDED_COMMAND;
- per_cpu(update_queue[idx], cpu).val = MMUEXT_LOAD_GS;
- increment_index_and_flush();
- spin_unlock_irqrestore(&update_lock, flags);
-}
-
void xen_invlpg(unsigned long ptr)
{
int cpu = smp_processor_id();
HYPERVISOR_set_timer_op(
u64 timeout)
{
- unsigned long timeout_hi = timeout >> 32;
- unsigned long timeout_lo = timeout & 0xffffffff;
int ret;
__asm__ __volatile__ (
TRAP_INSTR
: "=a" (ret)
- : "0" ((unsigned long)__HYPERVISOR_set_timer_op),
- "D" (timeout_hi), "S" (timeout_lo)
+ : "0" ((unsigned long)__HYPERVISOR_set_timer_op), "D" (timeout)
: __syscall_clobber );
return ret;
extern void load_gs_index(unsigned);
#define __load_gs_index(index) \
- xen_load_gs((index))
+ HYPERVISOR_set_segment_base(SEGBASE_GS_USER_SEL, index)
/*
* Load a segment. Fall back on loading the zero
__asm__ __volatile__ (
TRAP_INSTR
: "=a" (ret), "=b" (ign1), "=c" (ign2)
- : "0" (__HYPERVISOR_set_timer_op), "b" (timeout_hi), "c" (timeout_lo)
+ : "0" (__HYPERVISOR_set_timer_op), "b" (timeout_lo), "c" (timeout_hi)
: "memory");
return ret;
__asm__ __volatile__ (
TRAP_INSTR
: "=a" (ret), "=b" (ign1), "=c" (ign2)
- : "0" (__HYPERVISOR_set_timer_op), "b" (timeout_hi), "c" (timeout_lo)
+ : "0" (__HYPERVISOR_set_timer_op), "b" (timeout_lo), "c" (timeout_hi)
: "memory");
return ret;
void toggle_guest_mode(struct exec_domain *ed)
{
ed->arch.flags ^= TF_kernel_mode;
- __asm__ __volatile__ ( "swapgs" );
+ __asm__ __volatile__ ( "mfence; swapgs" ); /* AMD erratum #88 */
update_pagetables(ed);
write_ptbase(ed);
}
/* If in kernel mode then switch the GS bases around. */
if ( n->arch.flags & TF_kernel_mode )
- __asm__ __volatile__ ( "swapgs" );
+ __asm__ __volatile__ ( "mfence; swapgs" ); /* AMD erratum #88 */
if ( unlikely(!all_segs_okay) )
{
"movl %0,%%ds; "
"movl %0,%%es; "
"movl %0,%%fs; "
- "movl %0,%%gs; swapgs; movl %0,%%gs"
+ "movl %0,%%gs; "
+ "mfence; swapgs; " /* AMD erratum #88 */
+ "movl %0,%%gs"
: : "r" (0) );
}
}
-long do_update_descriptor(
- unsigned long pa, unsigned long word1, unsigned long word2)
+long do_update_descriptor(unsigned long pa, u64 desc)
{
unsigned long pfn = pa >> PAGE_SHIFT;
struct desc_struct *gdt_pent, d;
struct exec_domain *ed;
long ret = -EINVAL;
- d.a = (u32)word1;
- d.b = (u32)word2;
+ *(u64 *)&d = desc;
LOCK_BIGLOCK(current->domain);
popq %r11 # CS
cmpw $__GUEST_CS32,%r11
popq %r11 # RFLAGS
+ cli # No interrupts after stack switch
popq %rsp # RSP
je 1f
sysretq
movq EDOMAIN_syscall_addr(%rbx),%rax
movq %rax,TRAPBOUNCE_eip(%rdx)
movw $0,TRAPBOUNCE_flags(%rdx)
- pushq restore_all_guest(%rip)
- jmp create_bounce_frame
+ call create_bounce_frame
+ jmp restore_all_guest
/* %rbx: struct exec_domain */
hypercall:
FLT12: movq %rax,(%rsi) # DS
2: subq $16,%rsi
movq XREGS_r11+8(%rsp),%rax
-FLT13: movq %rax,(%rsi) # R11
+FLT13: movq %rax,8(%rsi) # R11
movq XREGS_rcx+8(%rsp),%rax
FLT14: movq %rax,(%rsi) # RCX
/* Rewrite our stack frame and return to guest-OS mode. */
{
struct exec_domain *ed = current;
+ /* Canonicalise the base address. */
+ base &= VADDR_MASK;
+
switch ( which )
{
case SEGBASE_FS:
wrmsr(MSR_GS_BASE, base, base>>32);
break;
+ case SEGBASE_GS_USER_SEL:
+ __asm__ __volatile__ (
+ " swapgs \n"
+ "1: movl %k0,%%gs \n"
+ " mfence; swapgs \n" /* AMD erratum #88 */
+ ".section .fixup,\"ax\" \n"
+ "2: xorl %k0,%k0 \n"
+ " jmp 1b \n"
+ ".previous \n"
+ ".section __ex_table,\"a\"\n"
+ " .align 8 \n"
+ " .quad 1b,2b \n"
+ ".previous "
+ : : "r" (base&0xffff) );
+ break;
+
default:
return -EINVAL;
}
goto good;
/* The guest can only safely be executed in ring 3. */
- if ( (b & _SEGMENT_DPL) != 3 )
+ if ( (b & _SEGMENT_DPL) != _SEGMENT_DPL )
goto bad;
/* All code and data segments are okay. No base/limit checking. */
}
/* Per-domain one-shot-timer hypercall. */
-long do_set_timer_op(unsigned long timeout_hi, unsigned long timeout_lo)
+long do_set_timer_op(s_time_t timeout)
{
- struct exec_domain *p = current;
+ struct exec_domain *ed = current;
- rem_ac_timer(&p->timer);
+ rem_ac_timer(&ed->timer);
- if ( (timeout_hi != 0) || (timeout_lo != 0) )
- {
- p->timer.expires = ((s_time_t)timeout_hi<<32) | ((s_time_t)timeout_lo);
- add_ac_timer(&p->timer);
- }
-
- TRACE_5D(TRC_SCHED_SET_TIMER, p->domain->id, p->eid, p, timeout_hi,
- timeout_lo);
+ if ( (ed->timer.expires = timeout) != 0 )
+ add_ac_timer(&ed->timer);
return 0;
}
#define SEGBASE_FS 0
#define SEGBASE_GS_USER 1
#define SEGBASE_GS_KERNEL 2
+#define SEGBASE_GS_USER_SEL 3 /* Set user %gs specified in base[15:0] */
/*
* int HYPERVISOR_switch_to_user(void)
* mfn: Machine frame number to be reassigned to the FD.
* (NB. page must currently belong to the calling domain).
*/
-#define MMUEXT_PIN_L1_TABLE 0 /* ptr = MA of frame to pin */
-#define MMUEXT_PIN_L2_TABLE 1 /* ptr = MA of frame to pin */
-#define MMUEXT_PIN_L3_TABLE 2 /* ptr = MA of frame to pin */
-#define MMUEXT_PIN_L4_TABLE 3 /* ptr = MA of frame to pin */
-#define MMUEXT_UNPIN_TABLE 4 /* ptr = MA of frame to unpin */
-#define MMUEXT_NEW_BASEPTR 5 /* ptr = MA of new pagetable base */
-#define MMUEXT_TLB_FLUSH_LOCAL 6 /* ptr = NULL */
-#define MMUEXT_INVLPG_LOCAL 7 /* ptr = VA to invalidate */
-#define MMUEXT_TLB_FLUSH_MULTI 8 /* ptr = NULL; mask = VCPUs to flush */
-#define MMUEXT_INVLPG_MULTI 9 /* ptr = VA to inval.; mask = VCPUs */
+#define MMUEXT_PIN_L1_TABLE 0
+#define MMUEXT_PIN_L2_TABLE 1
+#define MMUEXT_PIN_L3_TABLE 2
+#define MMUEXT_PIN_L4_TABLE 3
+#define MMUEXT_UNPIN_TABLE 4
+#define MMUEXT_NEW_BASEPTR 5
+#define MMUEXT_TLB_FLUSH_LOCAL 6
+#define MMUEXT_INVLPG_LOCAL 7
+#define MMUEXT_TLB_FLUSH_MULTI 8
+#define MMUEXT_INVLPG_MULTI 9
#define MMUEXT_TLB_FLUSH_ALL 10
#define MMUEXT_INVLPG_ALL 11
#define MMUEXT_FLUSH_CACHE 12
-#define MMUEXT_SET_LDT 13 /* ptr = VA of table; val = # entries */
+#define MMUEXT_SET_LDT 13
#define MMUEXT_REASSIGN_PAGE 14
#define MMUEXT_NEW_USER_BASEPTR 15
projects / xen.git / commitdiff